I realize this is a little late, but why was the hardware MUX fail-safe removed going from APM1 to APM2?
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I realize this is a little late, but why was the hardware MUX fail-safe removed going from APM1 to APM2?
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It didn't do anything we couldn't do in software on the new 32U2 chips in APM2, and we wanted to lower chip count, cost and complexity. The software MUX has been working great.