This is the third part of a three-part posting on chip design and how to reconcile it with the open source and DIY movements. (Part 1 is here and part 2 is here.) In this part I will discuss economics- How much does it actually cost to fabricate a chip? Can batching be used to make the cost accessible to a group of (hypothetical) casual chip designers?



Once a chip design is “taped out”, the chip foundry who manufactures them first creates a set of masks- anywhere from around 15 to upwards depending on the design and the manufacturing process. These are for a photolithography process that is vaguely similar to those used in PCB manufacture, however for chips the masks are both more precise and more expensive.

I won’t give exact costs or list specific foundries, but I’ve seen masks cost anywhere from under $10k to over $50k for a complete set. This is for a 0.5um or 0.6um process. Obviously the masks for the latest 32nm process would be much more.



Typically in chip design the foundry creates a set of masks for a “reticle”, a box-like region that gets replicated over and over across a whole wafer using a stepping process. A wafer itself is a disc of silicon less than a millimeter thick but generally tens of centimeters in diameter.

The typical reticle size I use is about 21mm x 21mm. (The masks themselves are much larger than this but the image is optically reduced during the manufacturing process.) You can fill up that reticle pretty much any way you want- you can put in a single 21mm x 21mm chip. If your chip size is just 2mm x 2mm you can put in a 100 of these into the reticle, so every reticle gets you 100 chips. You could also put in 100 different designs. This is where batching would come in.



There are companies that provide batching services. One of the oldest is the MOSIS service, run by ISI of the University of Southern California. MOSIS was set up originally with DARPA and NSF grants as a way to bring chip design to universities, and give students the ability to design and fabricate a chip, either as a classroom exercise or for a research grant. MOSIS also offered their services to industry. To this day they still offer these services and actually serve as a “store front” for several major chip foundries (ON-Semiconductor, TSMC, IBM, and others) for customers who want to prototype chips without paying for a whole set of masks.

The economics are essentially that everyone shares the cost of the tooling. Let’s say a mask set for a reticle has 10 different designs and cost $20k to make (a somewhat made up number)- that comes down to $2k per design- a much more reasonable number!

There are other services similar to MOSIS, and there are also individual companies that offer “multi-project runs” specifically for smaller customers that want to batch-prototype chips. So the batching concept is clearly established. In fact, whenever I do a run of silicon at Centeye I also place multiple designs on one reticle to get the most for my money.


Hypothetical Cost Breakdown

So let’s suppose a company wanted to get into the chip batching business. Let’s say the company decides to accept 2mm x 2mm size chips, and place 100 different designs onto a reticle. (The remaining 1mm slivers could be used for test circuits and quality control…) Looking at pure costs alone (e.g. neglecting stuff like “overhead”, “labor”, and “profit”), the numbers might look like this:


Mask set for a 21mm x 21mm reticle: $20,000

6”/150mm diameter wafers, set of 10 (approx 30+ reticles per wafer): $10,000

Dicing the wafer up into chips: $500 per wafer


First consider prototype quantities- I don’t know of any foundry that will make a single wafer- typically a set of wafers are manufactured in case one or a couple of them fail quality assurance inspections. For initial prototyping you would end up dicing just one wafer. Next comes packaging- most customers are not equipped to work with bare die, so they would probably want the chips in a DIP or similar package that they can then solder to a board or press into a breadboard- this would probably cost at most $20 per chip, at cost. Total cost per customer: ($20k + $10k + $500)/100 = $305 for about 30 chips, plus $20 per chip packaged.

Next let’s consider a slightly higher quantity price break, by dicing up all 10 wafers. The total cost per customer rises to ($20k + $10k + 10 x $500) = $350 for about 300 chips, not including packaging.

These numbers are encouraging. Of course, we have to assume 100 such customers can be found, and we have to consider the other costs to stay in business, but the above numbers should give you a starting point.


So where does that put us?

Once we factor in the cost of doing business, we get upwards to a thousand dollars for a batch-run prototype chip. This is a stiff amount compared to a batch-fabbed PCB. But it is not impossible- This amount is easily within the budget of a Kickstarter project, and there are hobbyists that would be willing to spend this amount on a chip fab. Certainly small companies could spend this amount. Also note that due to the nature of the chip manufacturing process, there could be several hundred individual chips available for use (or sale) if the design works. (There are a number of caveats, of course, which I didn’t mention here, but can discuss below if there is interest.)

I think one of the challenges, though, is overcoming the fear of spending money on a fabrication that doesn’t work. Getting back a PCB that doesn’t work is never fun; the stakes are higher for chips because of both the higher cost and the long lead times (generally six weeks or more). This is where the combination of good design tools and good design practices can help out- I think the “abstract layout” workaround mentioned in my last post, properly executed, could make “probability of success” sufficiently high for the DIY crowd.


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  • Hi Geoffrey, thank you for your suggestions. I am new to analog circuit design. I like your idea of integrating several designs. This isn't part of a curriculum and I am on my own. I haven't mastered analog design as such but know the basics of MOS physics. The idea is to learn analog IC design through this exercise. I intend to do the transistor level design and simulate it using LTSpice before going ahead with the layout, verification & the rest. Are there any sample designs/step-by-step tutorials available that you may know of? If so, it could help me get started on this.
    Coming to the cost part of it, is it possible for 'individuals' to get a chip fabbed at 0.5u ON process at educational rates? Last I checked a commercial design at this process node from MOSIS costs approximately $4500.
  • Hi Davis- This is great! Are you doing this as part of a class or is this something you want to do on your own? Regarding the $980 fab- that was the price for an MPW fab on a 1.2u process as offered by the MOSIS service back in 2000. They don't offer MPW runs in that process anymore. But they do have "educational rate" MPWs for their 0.5u process that, I believe, are less than the $2500 quote you got from CMP. You *might* be able to get in on one of those runs- This is the ON-Semi C5 process. https://www.mosis.com/vendors/view/on-semiconductor/c5 

    One thing to consider, if you haven't thought of it already- you can place several different designs onto the same chip to test more ideas. This should work for op-amps since those are typically much smaller than the size of a chip. Each design would get it's own pads of course.

    The MOSIS Service: Vendors : ON Semiconductor : C5
    MOSIS Is An Multi-Project Wafer (MPW) Integrated Circuit (IC) Fabrication Service Provider
  • @Geoffrey: Hi , I am a newbie , I am late for comment, sorry for that.

    I am immensely passionate about circuit design & would like to design an analog chip (opamp) just for the pleasure of doing it. I was deeply intrigued by your post, particularly as you mentioned the fab cost to be between $980 to $58k. Could you please elaborate on the MPW service you used to get a chip made for as low as $980 since the cheapest service I could find is a 0.35 μm CMOS process for about $2500 at present currency rates. That includes 25 die, with five of them packaged, and a die-size up to 3mm^2. Its offered by a french MPW service called CMP.   http://cmp.imag.fr/products/ic/?p=prices

  • Developer

    I know I'm two weeks later than everyone else but I really enjoyed these 3 articles that each touched on a different aspect of open source chip design.


    A few things surprised me..like the fact that you get back a 'die' instead of a dip package or a surface mounted chip but it makes sense that it's not that easy!  Also learning that at the lowest level you actually draw the parts in the material is somehow scary.


    I'd thought it was just the complexity and the requirement to make a huge number of chip (that the associated cost) that was keeping hobbyists from getting involved.  It's too bad that there's these this protectiveness from the foundries as well.


    The series made me want to design a chip!

  • Exploring the idea at all kind of leaves common sense and more particle aspects behind.  The R&D costs far exceed the cost of prototyping/production.


    Are Arlene, Don, Bret, and Cindy really going to bust their brains for a year or better just to come up with a design that does 5% of what the crappiest chip out there does... and then pay 20,000% more for it (even at semi-scale production)?


    Not trying to be a downer...

  • @Wolfgang: Thanks! Now THAT is ambitious! (Makes me wonder what Jack Kilby's notebook looked like...)

  • Great posts, thanks! Wanted to point you to Andrew Zonenberg's homecmos project, different angle but same spirit of openess...


    800x zoom, 20um line/space nominal dimension: http://i.imgur.com/a1NgR.jpg

    Keep your informative posts coming, thanks again!

  • @Ritchie- That would be an expensive fab! I'm sure that image sensor companies would be making such a chip before too long, if they aren't already.

  • I am curious- What type of designs would people here like to see "go through to the DIP"? What type of chips would people want to make? Or are people more interested in tinkering.

    I'll share one observation from my past work designing and using chips: Our chips tend to be specialized image sensors, most of which have added electronics to do some additional processing in the analog domain. This means we still have to attach the chips to optics and to a processor running firmware before we can get the chip to do anything useful. Typically for every day we spend designing a chip, we can spend between ten and fifty days integrating it with a system and learning how to get the most use out of it. This is probably because I tend to design the chips to be hackable rather than fixed in function. But from a business perspective, if you include such "labor" in the overall cost to design a system, the cost of the chip can be quite small.

    As a side comment: One of the reasons we are moving towards opening parts of the chip design- specifically by publishing schematics- is to make the chips easier for others to hack.

  • There is only one reason I would consider this sort of purchase and that would be the ability to create camera chips (CCD or CMOS). I would love to design a Ritchie Proof camera that throws out 1920x1080 with enough speed to hit 100FPS. I'm no chip designer so it would be yet more wasted money more likely but until camera people listen I can but hope.

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