The SF40 controller board

In systems that need precise timing and accurate waveform generation it is sometime necessary to separate out the time-critical elements from the non-realtime processing. Even though interrupts and realtime operating systems can improve the timing response of a processor system, microprocessors are fundamentally sequential execution devices which makes it very difficult for them to transition rapidly between different time critical operations without introducing unpredictable delays. Also, unexpected software excursions to service rarely used routines can leave time sensitive peripherals hanging.

As an example of a time critical system, the SF40 LiDAR has to synchronize the precisely timed data stream from the laser with the position of the motor. At the same time, alarm updates and requests for navigation information from the flight controller introduce asynchronous demands on the processor.

The SF40 includes a three phase brushless DC motor to drive the laser sensor. This motor needs three, pulse-width-modulated (PWM) signals to synthesize the 120 degree phase shifted sine waves needed to produce the right magnetic field patterns in the motor. Whilst hardware PWM generators are now common on most microprocessors, they require software intervention to change their pulse width values and things start to get busy if you want to produce continuous, high resolution, smooth rotation in the motor. Adding in active control of the motor speed (5:1 control) and torque (100:1 control) and compensating for changes in battery voltage (6.5V to 30V) makes driving the motor even more complicated.

The SF40 separates out the non-realtime microprocessor functions from the real-time signal generation needed to drive the motor. It does this by combining FPGA fabric with an ARM Cortex-M3 microprocessor subsystem (MSS) in a SmartFusion chip from MicroSemi.

The MSS has numerous hardware resources that unload the processor from actions like buffering communications with the flight controller whilst simultaneously allowing interrupt driven communications with the laser.


The microprocessor subsystem

The MSS has a clock conditioning circuit (CCC) with a number of different clock signals that can be configured to give the best PWM frequency, processor clock speed and in this case there is also a clock to drive a servo.


The clock conditioning circuit

The MSS also has an analog co-processor engine (ACE) that continually monitors currents and voltages around the system as well as filters and rescales them. The ACE runs autonomously so the processor only needs to ask for the results whenever it needs them.


The control panel for the analog computing engine

The MSS is connected to the FPGA fabric through direct port pins and an APB (advanced peripheral bus). The functional components within the FPGA fabric are made up using standard library parts and custom VHDL modules.


Top level architecture of the SF40

One of the key items in the architectural diagram is a two port RAM embedded in the FPGA fabric that allows the processor to create and store the high resolution, three phase waveforms needed by the motor. The RAM is initialized by the processor and thereafter the motor driver module in the FPGA fabric reads the waveforms as fast or as slowly as necessary to drive the motor at different speeds. Using the RAM in this way allows for on-the-fly changes in modulation depth which lets the SF40 maintain constant torque at different motor speeds and power supply voltages. 


VHDL code for generating precise PWM waveforms

By combining the hardware controls in the FPGA fabric with software running in the MSS, the SF40 is able to have the best of both worlds in terms of precise timing and waveform generation along with lots of asynchronous processing capacity. IMHO, this type of architecture should be used more often whenever reliable interaction is needed between high performance processing platforms and the real world :).

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  • Hi Gary, thanks for the comments. There's a link to a video somewhere below where you can see the acceleration and deceleration of the motor under FPGA control - BTW this is with audio so there really is almost no noise. I changed the speed by typing a command on my keyboard and you can see how remarkably smooth the motion and transitions are.

    There's just a little torque reaction at the peak acceleration points because the unit automatically increases the torque of the motor if you ask it to handle some kind of rotational acceleration. Once it's at a steady speed it drops the torque to keep the motor cool and reduce battery loading.

    What blows me away is that it will do this absolutely consistently at any battery voltage from 6.5V to 30V with no perceptible difference in the performance, torque or power dissipation. Add into this mix that it can perform live navigation and you can see that this kind of architecture is deceptively powerful :).



  • Hi LD,

    Really great development and an excellent presentation of modular architecture dealing with the blending of multiple fast continuous real time events and controls and responses.

    PGAs are really a necessary component of laser ranging devices and the SF40 appears to integrate one very nicely, I will be looking more closely at it, thank you for this article.

    Miles ahead as usual.



  • It's possible that there are some three phase motor driver cores available but unfortunately the free IP cores that can be used to generate PWM signals are not suitable for driving a motor in the way needed for this project. Remember the purpose of the design is to take away the real-time intervention by the processor which means that the motor driver core needs to be able operate independently. This is achieved by interfacing it to a RAM block and getting the driver core to manage the full sine wave generation.

    In terms of design complexity this one is not particularly difficult. The purpose of the blog post was to give people an idea of how to separate out real-time activities to free up processing capacity.

  • Thanks for your introduction. I have experience in xilinx and orcad tools. you have used PWM part for laser beam forming, and it's a free IP, right? no other particular IP needed expect fabric specific purpose?

  • @Jerry, when we talk about IP in the context of FPGA design it usually refers to the "cores" that are components of the design. For example, in the SF40 there is a standard library part for the data bus in the FPGA fabric, this is a "free core" whereas the three phase PWM driver for the motor has been written specifically for this project and is not freely available. In the FPGA world it is common to offer specialized "IP cores" for sale.

    Semiconductor intellectual property core
    In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or integrated circuit (commo…
  • what particular IP has been used in this Lidar design? i mean expect those clocking/micro processor/bus for proprietary architecture are different of course, what particular algorithm/control IP has been used in your design?

  • @Patrick, thanks for the comments. If I understand your question correctly, Libero comes with a comprehensive IP library and, although you can buy specialized modules if you need them, I have found that it's easy to make your own from the library parts and some VHDL coding. Once the project is complete the whole system can be locked using dual AES128 bit encryption keys making it impossible for anyone to clone your design. At this time the IP for the SF40 is locked but if we get enough interest we might make it open source.

    In practice, you can use the free "Gold" licensed version of Libero and a JTAG programmer to be up and running with SmartFusion as easily and cheaply as any other processor platform. Since it uses the Eclipse programming environment and the MSS is standard ARM at the core, software development is also easy.

    A really important feature that I haven't mentioned is that designing hardware in an FPGA environment allows you to run comprehensive simulations before committing to a PCB layout. These simulations are so good that the design works straight out of the box reducing development time dramatically.

    It is possible to run an RTOS on the MSS making it theoretically possible to build a flight controller with hardware accelerators on-board using one of the bigger SmartFusion 2 family of chips. If I get some time one day I might give it a go :).

  • Thanks for this very interesting visit inside the unit. 

    The Smartfusion SOC is a very interesting piece of hardware, and the Analog Compute Engine makes it very attractive for signal processing.  Having all the IO  (2x I2C-SPI-2x UART) , Memory and Timers embedded within the Microcontroler Subsystem really gives a lot of headroom for hardware fabric design ( you don't have to use half of the gates for these functions) and the internal memory really simplify the integration. 

    At 30$ , this SOC is a real good match for this type of application, you really made a nice product.

    LIBERO design suite looks more intuitive than Xilinx VIVADO, at  half the price,  the only question remaining, how the IP are licenced ?

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