The SF40 controller board
In systems that need precise timing and accurate waveform generation it is sometime necessary to separate out the time-critical elements from the non-realtime processing. Even though interrupts and realtime operating systems can improve the timing response of a processor system, microprocessors are fundamentally sequential execution devices which makes it very difficult for them to transition rapidly between different time critical operations without introducing unpredictable delays. Also, unexpected software excursions to service rarely used routines can leave time sensitive peripherals hanging.
As an example of a time critical system, the SF40 LiDAR has to synchronize the precisely timed data stream from the laser with the position of the motor. At the same time, alarm updates and requests for navigation information from the flight controller introduce asynchronous demands on the processor.
The SF40 includes a three phase brushless DC motor to drive the laser sensor. This motor needs three, pulse-width-modulated (PWM) signals to synthesize the 120 degree phase shifted sine waves needed to produce the right magnetic field patterns in the motor. Whilst hardware PWM generators are now common on most microprocessors, they require software intervention to change their pulse width values and things start to get busy if you want to produce continuous, high resolution, smooth rotation in the motor. Adding in active control of the motor speed (5:1 control) and torque (100:1 control) and compensating for changes in battery voltage (6.5V to 30V) makes driving the motor even more complicated.
The SF40 separates out the non-realtime microprocessor functions from the real-time signal generation needed to drive the motor. It does this by combining FPGA fabric with an ARM Cortex-M3 microprocessor subsystem (MSS) in a SmartFusion chip from MicroSemi.
The MSS has numerous hardware resources that unload the processor from actions like buffering communications with the flight controller whilst simultaneously allowing interrupt driven communications with the laser.
The microprocessor subsystem
The MSS has a clock conditioning circuit (CCC) with a number of different clock signals that can be configured to give the best PWM frequency, processor clock speed and in this case there is also a clock to drive a servo.
The clock conditioning circuit
The MSS also has an analog co-processor engine (ACE) that continually monitors currents and voltages around the system as well as filters and rescales them. The ACE runs autonomously so the processor only needs to ask for the results whenever it needs them.
The control panel for the analog computing engine
The MSS is connected to the FPGA fabric through direct port pins and an APB (advanced peripheral bus). The functional components within the FPGA fabric are made up using standard library parts and custom VHDL modules.
Top level architecture of the SF40
One of the key items in the architectural diagram is a two port RAM embedded in the FPGA fabric that allows the processor to create and store the high resolution, three phase waveforms needed by the motor. The RAM is initialized by the processor and thereafter the motor driver module in the FPGA fabric reads the waveforms as fast or as slowly as necessary to drive the motor at different speeds. Using the RAM in this way allows for on-the-fly changes in modulation depth which lets the SF40 maintain constant torque at different motor speeds and power supply voltages.
VHDL code for generating precise PWM waveforms
By combining the hardware controls in the FPGA fabric with software running in the MSS, the SF40 is able to have the best of both worlds in terms of precise timing and waveform generation along with lots of asynchronous processing capacity. IMHO, this type of architecture should be used more often whenever reliable interaction is needed between high performance processing platforms and the real world :).