This is the third part of a three-part posting on chip design and how to reconcile it with the open source and DIY movements. (Part 1 is here and part 2 is here.) In this part I will discuss economics- How much does it actually cost to fabricate a chip? Can batching be used to make the cost accessible to a group of (hypothetical) casual chip designers?



Once a chip design is “taped out”, the chip foundry who manufactures them first creates a set of masks- anywhere from around 15 to upwards depending on the design and the manufacturing process. These are for a photolithography process that is vaguely similar to those used in PCB manufacture, however for chips the masks are both more precise and more expensive.

I won’t give exact costs or list specific foundries, but I’ve seen masks cost anywhere from under $10k to over $50k for a complete set. This is for a 0.5um or 0.6um process. Obviously the masks for the latest 32nm process would be much more.



Typically in chip design the foundry creates a set of masks for a “reticle”, a box-like region that gets replicated over and over across a whole wafer using a stepping process. A wafer itself is a disc of silicon less than a millimeter thick but generally tens of centimeters in diameter.

The typical reticle size I use is about 21mm x 21mm. (The masks themselves are much larger than this but the image is optically reduced during the manufacturing process.) You can fill up that reticle pretty much any way you want- you can put in a single 21mm x 21mm chip. If your chip size is just 2mm x 2mm you can put in a 100 of these into the reticle, so every reticle gets you 100 chips. You could also put in 100 different designs. This is where batching would come in.



There are companies that provide batching services. One of the oldest is the MOSIS service, run by ISI of the University of Southern California. MOSIS was set up originally with DARPA and NSF grants as a way to bring chip design to universities, and give students the ability to design and fabricate a chip, either as a classroom exercise or for a research grant. MOSIS also offered their services to industry. To this day they still offer these services and actually serve as a “store front” for several major chip foundries (ON-Semiconductor, TSMC, IBM, and others) for customers who want to prototype chips without paying for a whole set of masks.

The economics are essentially that everyone shares the cost of the tooling. Let’s say a mask set for a reticle has 10 different designs and cost $20k to make (a somewhat made up number)- that comes down to $2k per design- a much more reasonable number!

There are other services similar to MOSIS, and there are also individual companies that offer “multi-project runs” specifically for smaller customers that want to batch-prototype chips. So the batching concept is clearly established. In fact, whenever I do a run of silicon at Centeye I also place multiple designs on one reticle to get the most for my money.


Hypothetical Cost Breakdown

So let’s suppose a company wanted to get into the chip batching business. Let’s say the company decides to accept 2mm x 2mm size chips, and place 100 different designs onto a reticle. (The remaining 1mm slivers could be used for test circuits and quality control…) Looking at pure costs alone (e.g. neglecting stuff like “overhead”, “labor”, and “profit”), the numbers might look like this:


Mask set for a 21mm x 21mm reticle: $20,000

6”/150mm diameter wafers, set of 10 (approx 30+ reticles per wafer): $10,000

Dicing the wafer up into chips: $500 per wafer


First consider prototype quantities- I don’t know of any foundry that will make a single wafer- typically a set of wafers are manufactured in case one or a couple of them fail quality assurance inspections. For initial prototyping you would end up dicing just one wafer. Next comes packaging- most customers are not equipped to work with bare die, so they would probably want the chips in a DIP or similar package that they can then solder to a board or press into a breadboard- this would probably cost at most $20 per chip, at cost. Total cost per customer: ($20k + $10k + $500)/100 = $305 for about 30 chips, plus $20 per chip packaged.

Next let’s consider a slightly higher quantity price break, by dicing up all 10 wafers. The total cost per customer rises to ($20k + $10k + 10 x $500) = $350 for about 300 chips, not including packaging.

These numbers are encouraging. Of course, we have to assume 100 such customers can be found, and we have to consider the other costs to stay in business, but the above numbers should give you a starting point.


So where does that put us?

Once we factor in the cost of doing business, we get upwards to a thousand dollars for a batch-run prototype chip. This is a stiff amount compared to a batch-fabbed PCB. But it is not impossible- This amount is easily within the budget of a Kickstarter project, and there are hobbyists that would be willing to spend this amount on a chip fab. Certainly small companies could spend this amount. Also note that due to the nature of the chip manufacturing process, there could be several hundred individual chips available for use (or sale) if the design works. (There are a number of caveats, of course, which I didn’t mention here, but can discuss below if there is interest.)

I think one of the challenges, though, is overcoming the fear of spending money on a fabrication that doesn’t work. Getting back a PCB that doesn’t work is never fun; the stakes are higher for chips because of both the higher cost and the long lead times (generally six weeks or more). This is where the combination of good design tools and good design practices can help out- I think the “abstract layout” workaround mentioned in my last post, properly executed, could make “probability of success” sufficiently high for the DIY crowd.


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  • I would be of the few who would like to see a design through to the dip. If we can put together a list or group to help get it made.

    Also another great post.
  • Very interesting and informative, thanks!

  • @Frederic- Both of your comments are absolutely correct.

    The dicing issue is one of the caveats I was going to bring up. Yes, wafers are still mostly diced mechanically with a saw. Basically the saw cuts the wafer up first into strips, and then makes additional cuts in the orthogonal direction to make the chips. Thus the chips actually have to line up perfectly on a grid. (The picture above is misleading a bit, but I didn't want to get too much into detail at first.)

    You *can* actually have them off grid a bit, like in the picture above, but then dicing costs more because every other strip would have to be lifted out and remounted. Think $1500 per wafer for dicing rather than $500.

    There are some companies offering "laser dicing" which would get around this issue, but probably at too high a price point to be of interest.

    As for the process options- Yes this is an issue. I think an 80/20 analysis would show, though, that most people's needs can be met with a limited set of options. (I've never needed more than basic CMOS and 2 layers of polysilicon, for example.) But this does make it difficult for people who want, for example, to add flash memory to their chip or implement transistors that operate at 50V.

  • I know it is expensive, especially if you are the one trying to put together the price of a new car for a full fab. The good news though is that once you have the masks you can churn out chips for dollars or less apiece, albeit in huge quantity.

    I agree $99@ would be great! It might be possible if you use a very large (and old) feature size, but I haven't looked into that.

    As for the chip industry- rather than being "held back", industry has adapted- for digital we have FPGAs- the design resides in software, and can stay there forever if one doesn't want to actually make a chip. (Also, XMOS has hit a nice point between FPGAs and regular processors.) However for analog I am not aware of any commercially viable FPAAs (field programmable analog arrays), the analog counterpart to FPGAs. Analog signals can be quite messy and complicated, compared to the clean 1/0 of digital.

  • the principle of your cost analysis relies on the fact that all the chips in the reticle can be diced out of the wafer. in multi project environments it is not often the case. so far dicing ( as far as I know) is still done with a mechanical saw so when you dice the only thing you can do is a straight line across the wafer. if ALL the edges of the different designs are not aligned you have to destroy some chips to dice out others. in the example you show in your picture, the vertical cuts are fine but if you choose for example to get Cindy and Don, Bret's chip will be cut in the middle. multi project programs try to limit that by creating a "grid" that your design has to stick to ( eg a 1mm pitch grid, so if your design is 2.07x 3.55=7.35 it will fit into a 3x4=12 block and you will pay for 12!) but even with that if you have a mix of chips with different sizes you will have to scrap a lot of chips.


    the other aspect around finding multiple customers is they have to share the same process. this is not limited to feature size ( eg CMOS 0.6µm ) but also on the option side. most of the processes have a long list of options lots of which are not compatible with each other eg number of metal layers and metal stack, mix of transistors vt, analog or embedded flash, wire bonding or flipchip... so the difficulty is to find enough customers with a compatible set of requirements to fill a reticle. and as the process evolves the reticle is bigger ( 26x32 for 12" wafers ).


    anyway at the right price point there are lots of people potentially interested.

  • sounds very expensive - enough to be holding back the industry.

    $99 per test would be a good goal to set.

    Many of those costs suffer from inadequate downward scaling.


  • Very nice explanation.But it also points out the cost of chip design and manufacture remains very high.

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